The NoC is configured using the AXI NoC IP. The IP acts as logical representations of the NoC. The AXI NoC IP supports the AXI memory-mapped protocol, and the AXIS NoC IP supports the AXI4-Stream protocol. A Versal adaptive SoC design can include multiple instances of each type of IP.
The DDR memory controller is integrated into the AXI NoC IP. An instance of the AXI NoC can be configured to include one, two, or four instances of the DDR memory controller. You must use the NoC IP to communicate with the integrated DDR memory controller. During the validate step, the Versal NoC compiler is run on the unified traffic specification. After validation, the NoC Viewer window allows you to review and edit the NoC solution.
For configuration details on the NoC and related IP as well as details on the system address map, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).