CIPS Verification IP - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2022.2 English

The Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) supports the functional simulation of Versal ACAP applications. It is targeted to enable the functional verification of programmable logic (PL) by mimicking the processor system (PS)-PL interfaces and OCM memories of PS logic. This VIP is delivered as a package of SystemVerilog modules. VIP operation is controlled by using a sequence of SystemVerilog tasks. For more information, see the Versal ACAP CIPS Verification IP Data Sheet (DS996).