Clocking - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2022-10-19
Version
2022.2 English

To achieve optimal clocking results in the Versal architecture, Xilinx highly recommends the following:

  • Use the Clocking Wizard to configure the Versal ACAP clock management primitives. Relying on the Vivado tools to migrate your clock management functions from a previous architecture will likely result in a sub-optimal configuration. For more information, see the Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321).
  • Review the physical locations of clock management primitives in Versal ACAP versus your clocking topology used in a previous architecture.

For more information about designing your clock network for your design, see the Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387). For more information on features and locations of the clock management primitives in Versal devices, see the Versal ACAP Clocking Resources Architecture Manual (AM003).

Although Versal devices have clocking features similar to UltraScale devices, you must be aware of the following important migration considerations.

Clock Management Functions

  • The clock management functions are provided by the MMCME5, XPLL, and DPLL primitives in Versal devices. The clock management primitives in Versal devices contain additional deskew logic features when compared against similar primitives contained within UltraScale devices.
  • The location of the clock management primitives in Versal devices are no longer in a regular structure when compared to the columnar architecture in UltraScale devices, and the primitives are only placed where required in Versal devices. In some scenarios, this can result in limited placement flexibility when migrating to a Versal device, and you must carefully review your clock structure during migration.
  • The UltraScale+ device primitives migrate to Versal device primitives as follows:
    • The UltraScale+ device primitive MMCME4_ADV migrates to the MMCME5 Versal device primitive. The MMCME5 does not support ZHOLD compensation. The MMCME5 settings as a result of a migration from a previous architecture are likely to be sub-optimal, and Xilinx recommends using the Clocking Wizard to directly configure the MMCME5 for optimal performance in the Versal architecture.
    • The UltraScale+ device primitive PLLE4_ADV migrates to the XPLL Versal device primitive. The XPLL settings as a result of a migration from a previous architecture are likely to be sub-optimal, and Xilinx recommends using the Clocking Wizard to directly configure the XPLL for optimal performance in the Versal architecture.

Global Clock Buffers

  • Global clock buffers from previous architectures, such as BUFGCE, BUFGCE_DIV, BUFGCTRL, BUFG_PS, and BUFG_GT, automatically migrate to the Versal architecture.
  • New multi-clock buffer (MBUFG) primitives in Versal devices allow for clock division at the leaf level to reduce clock track utilization and improve timing on synchronous clock domain crossings.

Clock Routing Resources

  • Versal devices have a clock routing structure similar to UltraScale devices, where global clocking is used throughout the device but the loads can be placed regionally or globally.
  • Versal devices do not have a columnar I/O architecture, and there are only 12 horizontal routing tracks in clock regions without XPIO banks. Clock regions with XPIO banks have 24 horizontal routing tracks.