DSP - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2022-10-19
Version
2022.2 English

The Versal ACAP includes the DSP58 slice, which is a superset of and backward compatible with the UltraScale+ device DSP48E2 slice. In addition, the Versal ACAP DSP Engine supports floating point operations in a single DSP58 slice and can combine two back-to-back DSP58 slices with dedicated interconnect to build an 18-bit complex multiplier or complex multiply-accumulate (MACC). The DSPFP32 mode in Versal ACAP is supported through the Floating-Point Operator IP or the Vitis HLS tool. If you want to use this mode in your RTL design, update the Floating- Point Operator IP in your migrated design.

Xilinx supports automated migration of instantiated DSP primitives to the Versal ACAP legacy primitive (DSP48E5). To achieve higher performance and utilization, Xilinx recommends updating your RTL to the Versal ACAP RTL templates and resynthesizing your design.

For detailed architectural differences, see the Versal ACAP DSP Engine Architecture Manual (AM004).

Important: To take advantage of the Versal ACAP potential for increasing performance, consider which parts of the datapath can be ported from the PL into the AI Engines. You can optionally use the Model Composer and System Generator flows to compare the PL and AI Engine implementations for designs created with MATLAB® and Simulink® software. For more information, see the Vitis Model Composer User Guide (UG1483).