Design Closure - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2022-10-19
Version
2022.2 English

The Versal architecture introduces new hardware features that require additional considerations to reach design closure, including timing and performance closure. Similarly to previous Xilinx device architectures, the timing summary report is the signoff report for timing closure. Vivado Design Suite compilation tools provide guidance via the following reports:

  • Design rule checks prevent invalid hardware configurations (report_drc). Any such issue prevents the device image file generation and must be addressed.
  • Methodology checks improve the PL maximum operating frequency and identify common unsafe design structures, which can lead to hardware malfunction or instability (report_methodology, report_cdc). Critical and warning violations must be addressed to help timing closure and hardware stability.
  • Xilinx also recommends addressing critical warnings in the log files.
Important: To reduce timing closure iterations, you must review and address the timing violations as early as possible in the implementation flow, especially after synthesis and after placement.

Due to the heterogeneous nature of the Versal architecture, the design performance mostly depends on the NoC QoS, DDR memory access, and software efficiency in the PS and AI Engines in addition to the PL operating frequency and amount of pipelining. For information on timing, system performance, and power design closure, see the Versal ACAP System Integration and Validation Methodology Guide (UG1388).