Certain PMC and LPD peripherals can be routed via the extended multiplexed I/O (EMIO) interface through the PL to XPIO or HD I/O via I/O logic. For details on which peripherals can access the EMIO, see this link in the Versal Adaptive SoC Technical Reference Manual (AM011). The IO Configuration page in the CIPS IP is used to select which peripherals access the EMIO. Because EMIO uses I/O logic, the pin planning of the EMIO is completed using the traditional drag-and-drop pin planning in the Vivado Design Suite.
Power Tip: When pin planning the EMIO in the XPIO or HD I/O, consider the I/O voltage requirements of the peripheral interface in choosing the bank type. XPIO banks can support I/O voltages of 1.5V and below while HD I/O banks can support I/O voltages of 1.8V and above. For XPIO banks, the recommendation is to place the lower-speed I/O logic last to maximize package pin utilization, and this might leave a limited selection of I/O standards based on previously assigned I/O. You must ensure that your interface is feasible in the desired bank or banks. You can use the IBIS models to simulate the interface at your required speed with the I/O standard selected for your bank.