HLS Simulation - 2022.1 English

Versal ACAP Design Guide (UG1273)

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2022.1 English

HLS simulation exclusively tests HLS code and is an integral part of the HLS development process. The scope of this simulation is a single HLS kernel. Two abstractions are supported, untimed and RTL (cycle-accurate). These two abstractions are referred to as Csim and Cosim respectively. In the Cosim flow, the output of RTL code generated by the HLS compiler is automatically compared against the output of the original C code. The purpose of this flow is to verify the functional correctness of the RTL and to validate performance in a standalone context, independently of interactions with other functions.

HLS simulation is available through the Vitis unified software platform. For more information, see the Vitis HLS User Guide (UG1399).

Note: HLS simulation is possible in both the traditional design flow and the platform-based design flow.