The heterogeneous nature and performance of the Versal adaptive SoC necessitates a system-level high-bandwidth debug and trace solution. The high-speed debug port (HSDP) is a new feature in Versal adaptive SoC that provides unified, at-speed debugging and tracing of the various integrated, fabric-based, and processor blocks in the device under test (DUT). HSDP provides the option of performing debug and trace capture through a dedicated Aurora interface and a high-speed debug cable like SmartLynq+. High-speed debug over PCIe is also available for remote systems that are connected to a host through PCIe. HSDP functions are accessed via high-speed GT-based interfaces, such as the integrated Aurora interface in the PS block or the PCIe interface in the CPM block.
For more information, see the following resources:
- This link in the Versal Adaptive SoC Technical Reference Manual (AM011)
- SmartLynq+ Module User Guide (UG1514)
- System Design Example for High-Speed Debug Port (HSDP) with SmartLynq+ Module