You must use Vivado tools for synthesis and implementation. The Versal adaptive SoC includes new primitives that the Vivado synthesis tool infers.
Design closure techniques related to the device fabric are similar to previous device families. In addition to considerations for timing, congestion, and wirelength, the placer calls the NoC compiler again to account for modified NoC port location constraints or for merging traffic in Dynamic Function eXchange (DFX) mode while meeting the original QoS requirements, as shown in the following figure.
Figure 1. NoC Compiler Flow
