Integrating the Adaptable Subsystem Using a Standard Xilinx Platform - 2022.1 English

Versal ACAP Design Guide (UG1273)

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2022.1 English

After the AI Engine graph and PL kernels are independently developed and verified, you integrate them to form the adaptable subsystem. You can then verify and test the adaptable subsystem using a standard Xilinx platform (such as vck190). Xilinx platforms are pre-verified, which provides a stable foundation to build upon, allowing you to focus on the AI Engine graph and PL kernels. The Vitis environment design flow allows you to verify the adaptable subsystem using simulation or hardware boards as described in the following sections.

Note: The adaptable subsystem can be integrated and verified independently from the custom platform.