NoC simulation support is provided with behavioral models in either
SystemVerilog or SystemC. The simulation time with the SystemC model is much faster but
is cycle approximate and less accurate compared to the SystemVerilog model.
Note: You can select your preferred simulation
model using the IP Project Settings. Use the
rtl setting for SystemVerilog and the
tlm setting for SystemC. These settings
apply to the entire project.
Although you can use both the SystemC and SystemVerilog models to verify
functionality, the SystemVerilog model is recommended for performance analysis.
Performance analysis using the SystemVerilog model is within ±5% of hardware.
You can simulate the NoC using simulators in the Vivado tools or using the hardware emulation flow provided by the
For more information on the
NoC simulation settings and performance tuning, see this link
and this link
Versal Adaptive SoC Programmable Network on Chip and
Integrated Memory Controller LogiCORE IP Product Guide (PG313)
. For more information on the
AXI Traffic Generator, see the Versal Network on Chip Performance AXI Traffic
available from the GitHub repository.