RTL Design Flow - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2022-10-19
Version
2022.2 English

You can use the RTL design flow to create modules, instantiate IP, or assemble the top-level design, similar to previous architectures. However, you must follow Xilinx recommendations for using Versal device-specific blocks in the RTL design flow, including the CIPS and NoC IP. The CIPS IP provides access to device configuration features, and the NoC IP connects PL to one or several DDRMC hardened IP.

Xilinx highly recommends using the Vivado IP integrator to instantiate and configure the CIPS and NoC IP. However, you do not need to use the IP integrator for your entire design. The CIPS IP, NoC IP, and other memory-mapped components of the system can be configured in a block design using the IP integrator. The resulting block design can then be instantiated in the top-level RTL. Using this approach allows you to build the majority of your design using a traditional RTL flow.