Revision History - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2022.2 English

The following table shows the revision history for this document.

Section Revision Summary
10/19/2022 Version 2022.2
CIPS for PS, PMC, and CPM Added PMC power description in note.
System Design Types Updated System Design Types figure and removed no/custom platform.
Traditional Design Flow for Embedded Systems Updated AI Engine important note.
GT Added AM017 reference.
Report Power Updated to Power Design Manager.
Check Whether Design is Within Budget Updated to Power Design Manager.
Simulation Flows Added Supported Simulation Models and cycle approximate for AI Engine in Versal ACAP Blocks table.
AI Engine Simulation Added information on AXI traffic generators.
Hardware Emulation Added information on AXI traffic generators.
CIPS Verification IP Added new section.
On-Chip Memory Resources Added new memory blocks.
GT Added AM017 reference.
Classic SoC Boot Added parameter control note.
Security Updated Cumulative Secure Boot Operations table with HWRoT as N/A, A-HWRoT as N/A, S-HWRoT as N/A, and A-HWRoT + S-HWRoT as N/A.
PL Configuration and JTAG Added USR_ACCESS primitive description.
References Updated UG1275 to UG1556.
04/27/2022 Version 2022.1
NoC Added information on the NoC inter-die bridge (NIDB).
HSDP Added information on high-speed GT-based interfaces.
High-Speed Connectivity and Encryption Integrated IP Added new section.
AI Engine IP Updated section.
Using the Vitis Environment in the Design Flows Updated all sections.
Logic Simulation Using SystemC Models Added information on CPM.
Tandem Configuration Added new section.