Soft Memory Controllers - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2022-10-19
Version
2022.2 English

If your previous design used soft memory controller IP, you can either use the Versal ACAP soft memory controller IP or the integrated DDRMC. Xilinx recommends using the integrated DDRMC rather than using the Versal ACAP soft memory controller IP. In Versal ACAP, you can use the integrated DDRMC only via the NoC. The NoC and DDRMC have very high bandwidth but generally have a higher latency than a standalone soft memory controller. For some I/O banks, only the integrated DDRMC is supported. For more information on the DDRMC, see the Versal Architecture and Product Data Sheet: Overview (DS950).

If you are using the soft memory controller IP, you must regenerate the IP for Versal ACAP. In Versal ACAP, an I/O bank comprises nine nibbles, and each nibble has six pins. Depending on the device and package, some I/O banks or some nibbles in an I/O bank are dedicated for the integrated DDRMC. Soft memory controllers cannot use these dedicated pins. Pins dedicated for the integrated DDRMC are designated as YES in the package file under the column named DDRMC ONLY. The soft memory controllers can only use pins designated as NO. For more information on soft memory controller IP, including detailed information on pinout, see the following guides:

  • Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
  • Versal ACAP Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
  • Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)
  • Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)