System Monitor - 2022.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2022-10-19
Version
2022.2 English

The Versal ACAP provides system monitoring capabilities similar to UltraScale+ devices. In UltraScale+ device designs you instantiated the SYSMON IP on the PL side and used the System Management wizard to set up the register configuration for instantiation in the hardware description language (HDL). To migrate your design, you must manually remove the SYSMON IP from the design. In Versal ACAP, you enable the system monitor features in the CIPS IP Configuration wizard. Dynamic reconfiguration port (DRP) access is replaced by memory mapped registers. For more information, see the Versal ACAP System Monitor Architecture Manual (AM006).