The Vivado Design Suite is a key component in all Versal ACAP design flows. Following are the primary use models for the Vivado tools based on your design flow:
- Traditional design flows
- Creating RTL and IP designs
- Platform-based design flows
Important: If you are using the platform-based design flow, Xilinx provides standard platforms as starting points, which can be customized and regenerated by the Vivado IP integrator to better fit the target system application. For more information, see the Vitis Embedded Platforms tab of the Downloads page on the Xilinx website.
- Creating and packaging RTL kernels for use in the Vitis environment design flow
- Creating and generating platforms for use in the Vitis environment design flow
You can use the Vivado tools for design creation, implementation, and analysis of PL. Typical tasks include the following:
- Logic simulation
- Constraint definition and timing analysis
- NoC compilation
- I/O and clock planning
- Logic synthesis and implementation
- Visualization of design logic
- Design rule checks (DRC) and design methodology checks
- Implementation results analysis
- Power and thermal analysis
- Programming and debugging
Creating RTL and IP Designs
The Vivado tools support the traditional RTL and IP design flow, and the Vivado IP integrator is available to automate the assembly of your design. RTL developers must understand the new IP available in Versal ACAP and the requirements surrounding their usage, including the following:
- All designs require the CIPS IP, which contains the PMC used to boot the device. CIPS IP is also used to configure the PS peripherals and the SYSMON IP. For more information, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).
- The only way to access the DDRMCs on the device is through the NoC IP. For more information, see the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
- Hardware debug flows are different from previous devices. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Creating and Packaging RTL Kernels
You can use the Vivado tools to package RTL kernels for use by the Vitis linker. This option is available in the Vivado IP packager, which packages the IP into an XO file to be linked into the final design using the Vitis system linker. For more information about RTL kernels, including restrictions, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
Creating and Generating Platforms
Xilinx recommends the following:
- Include only essential Versal ACAP blocks and board interface IP in the platform
- Essential blocks: CIPS, NoC, AI Engine, Clocking wizard, interrupt controller
- Interface blocks: High-speed I/Os, memory controllers
- Map RTL modules that interact with AI Engine through streaming or memory mapped interfaces and other platform streaming interfaces to Vitis RTL kernels
Following are the benefits of this approach:
- Ensures the platform is highly reusable
- Promotes separation of tasks
- Improves the ability to automate the integration process
- Increases scope and opportunity for DFX