[Figure 1, callout 10-18]
The VCU128 evaluation board clock sources to the FPGA are listed in the following table.
| Clock Name | Clock Ref. Des. | Description |
|---|---|---|
| Memory Interface Clocks | ||
| DDR4 clock 100 MHz | U76 | SiTime SiT9120AI 3.3V fixed frequency 100.000 MHz (DDR4_CLK_100MHZ_P/N) |
| QDR4 clock 100 MHz | U96 | SiTime SiT9120AI 3.3V fixed frequency 100.000 MHz (QDR4_CLK_100MHZ_P/N) |
| RLD3 clock 100 MHz | U45 | SiTime SiT9120AI 3.3V fixed frequency 100.000 MHz (RLD3_CLK_100MHZ_P/N) |
| QSFP Interface Clocks | ||
| QSFP1 clock 156.250 MHz | U95 | Silicon Labs Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default. (QSFP1_SI570_CLOCK_P/N) |
| QSFP2 clock 156.250 MHz | U90 | Silicon Labs Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default. (QSFP2_SI570_CLOCK_P/N) |
| QSFP3 clock 156.250 MHz | U82 | Silicon Labs Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default. (QSFP3_SI570_CLOCK_P/N) |
| QSFP4 clock 156.250 MHz | U80 | Silicon Labs Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default. (QSFP4_SI570_CLOCK_P/N) |
| SMA GTY REFCLK and User Clock | ||
| QSFP GTY131 REFCLK1 SMA clock | SMA J24 (P)/SMA J26 (N) | Bank 131 series capacitor coupled SMA clock (SMA_REFCLK_INPUT_P/N) |
| FPGA U1 bank 67 GPIO user SMA clock | SMA J12 (P)/SMA J13 (N) | Bank 67 QBC direct connect GPIO SMA (SMA_CLK_OUTPUT_P/N) |
| QSFP1/2 recovery clocks | ||
| QSFP1/2 jitter attenuated clock | U87 | Silicon Labs Si5328B LVDS precision clock, multiplier/jitter attenuator. See Jitter Attenuated Clock (SI5328_CLOCK1/2_P/N) |
The following table lists the VCU128 clock sources-to-FPGA U1 connections.
| Clock Source Device/U#.Pin# | Schematic Net Name | I/O Standard | FPGA (U1) Pin |
|---|---|---|---|
| Memory Interface Clocks | |||
| SIT9120AI/U76.4 | DDR4_CLK_100MHZ_P | LVDS | BH51 |
| SIT9120AI/U76.5 | DDR4_CLK_100MHZ_N | LVDS | BJ51 |
| SIT9120AI/U96.4 | QDR4_CLK_100MHZ_P | LVDS | BJ4 |
| SIT9120AI/U96.5 | QDR4_CLK_100MHZ_N | LVDS | BK3 |
| SIT9120AI/U45.4 | RLD3_CLK_100MHZ_P | LVDS | F35 |
| SIT9120AI/U45.5 | RLD3_CLK_100MHZ_N | LVDS | F36 |
| QSFP Interface Clocks | |||
| SI570/U95.4 | QSFP1_SI570_CLOCK_P | 1 | P42 |
| SI570/U95.5 | QSFP1_SI570_CLOCK_N | 1 | P43 |
| SI570/U90.4 | QSFP2_SI570_CLOCK_P | 1 | T42 |
| SI570/U90.5 | QSFP2_SI570_CLOCK_N | 1 | T43 |
| SI570/U82.4 | QSFP3_SI570_CLOCK_P | 1 | Y42 |
| SI570/U82.5 | QSFP3_SI570_CLOCK_N | 1 | Y43 |
| SI570/U80.4 | QSFP4_SI570_CLOCK_P | 1 | AB42 |
| SI570/U80.5 | QSFP4_SI570_CLOCK_N | 1 | AB43 |
| SMA GTY REFCLK and User Clock | |||
| SMA J24.1 | SMA_REFCLK_INPUT_P | 1 | AA40 |
| SMA J26.1 | SMA_REFCLK_INPUT_N | 1 | AA41 |
| SMA J12.1 | SMA_CLK_OUTPUT_P | 2 | BK26 |
| SMA J13.1 | SMA_CLK_OUTPUT_N | 2 | BL25 |
| QSFP1/2 Recovery Clocks | |||
| SI5328B/U87.29 | SI5328_CLOCK1_P | 1 | R40 |
| SI5328B/U87.28 | SI5328_CLOCK1_P | 1 | R41 |
| SI5328B/U87.35 | SI5328_CLOCK2_P | 1 | W40 |
| SI5328B/U87.34 | SI5328_CLOCK2_P | 1 | W41 |
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