[Figure 1, callout 36]
The VCU128 board supports two of the seven
UltraScale™
FPGA configuration modes.
- Master SPI using the onboard 2 Gbit Quad SPI flash memory
- JTAG using:
- USB JTAG configuration port J2 (FTDI FT4232H bridge U8)
- Xilinx® platform cable 2 mm, keyed flat cable header (J4)
Each configuration interface corresponds to one or more configuration modes and bus widths as listed in the following table. The mode switches M2, M1, and M0 are on 4-pole DIP SW1 positions 2, 3, and 4, respectively. The FPGA default mode setting M[2:0] = 001, selecting the master SPI configuration mode.
| Configuration Mode | SW16 DIP Switch Settings (M[2:0]) | Bus Width | CCLK Direction |
|---|---|---|---|
| Master SPI | 1 | x1, x2, x4 | Output |
| JTAG | 101 | x1 | Not applicable |
The following figure shows mode switch SW1.
Figure 1. SW1 JTAG Settings
The mode pins settings on SW1 determine if the Quad SPI flash is used for configuring the FPGA. DIP switch SW1 also includes a system controller enable switch in position 1. See the UltraScale Architecture Configuration User Guide (UG570) for further details on configuration modes.