DDR4 Component Memory

[Figure 1, callout 4]

The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).

The 72-bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64, 65 and 66. The DDR4 0.6V VTT termination voltage (net DDR4_VTERM_0V6) is sourced from the TI TPS51200DR linear regulator U71. The DDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connections between the 72-bit interface DDR4 component memories and XCVU37P banks 64, 65, and 66 are listed in the following table.

The VCU128 DDR4 memory component interfaces adhere to the constraints guidelines documented in the “DDR3/DDR4 Design Guidelines” section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 board DDR4 memory component interface is a 40Ω impedance implementation.

For more information on the internal VREF, see the “Supply Voltages for the SelectIO Pins VREF” and the “Internal VREF” sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron DDR4 component memory, see the Micron MT40A512M16LY data sheet at the Micron Technology website.