GPIO Connections to FPGA U1

VCU128 Evaluation Board User Guide (UG1302)
Document ID
UG1302
Release Date
2022-05-06
Revision
1.2 English

The following table lists the GPIO connections to FPGA U1.

Table 1. GPIO Connections to FPGA U1
FPGA (U1) Pin Schematic Net Name

FPGA (U1) Direction

 I/O Standard Device
GPIO LEDs (Active-High) GPIO_LED signals are wired to LED driver U56
BANK 67 BH24 GPIO_LED_0 Output LVCMOS18 DS2
BANK 67 BG24 GPIO_LED_1 Output LVCMOS18 DS3
BANK 67 BG25 GPIO_LED_2 Output LVCMOS18 DS4
BANK 67 BF25 GPIO_LED_3 Output LVCMOS18 DS5
BANK 67 BF26 GPIO_LED_4 Output LVCMOS18 DS6
BANK 67 BF27 GPIO_LED_5 Output LVCMOS18 DS7
BANK 67 BG27 GPIO_LED_6 Output LVCMOS18 DS8
BANK 67 BG28 GPIO_LED_7 Output LVCMOS18 DS9
CPU reset pushbutton (active-high)
BANK 64 BM29 CPU_RESET Input LVCMOS12 SW4.3
GPIO SMA pair (applied voltage should not exceed 1.8V)
BANK 67 BH27 SMA_CLK_OUTPUT_P I/O LVCMOS18 J12.1
BANK 67 BJ27 SMA_CLK_OUTPUT_N I/O LVCMOS18 J13.1