[Figure 1, callout 25, 26]
The VCU128 evaluation board I2C bus implementation consists of I2C bus I2C0. The FPGA U1 HP bank 67 (VCCO VCC1V8) and system controller U42 bank 501 are wired to I2C0 via level-shifters. I2C bus I2C0 is routed to a 1-to-4 channel TI PCA9544A bus switch U55 (address 0x75) and a dual 8-bit port TI TCA6416A IO expander U65 (address 0x20). I2C bus I2C0 is also routed to a pair of 1-to-8 channel TI TCA9548A bus switches U53 (address 0x74) and U54 (address 0x76). The bus switches can operate at speeds up to 400 kHz. The VCU128 evaluation board I2C0 I2C bus topology is shown in the following figures.
Important: The TCA9548 U53 and U54
RESET_B pin 3 control signal IIC_MUX_RESET_B is connected to the I2C0 bus TCA6416A U65
port expander (Addr 0x20) port P05 pin 9. The IIC_MUX_RESET_B signal must be driven hi-Z
or High to enable I2C bus transactions with the target devices connected to U53 and
U54.
Figure 1. I2C0 Bus Topology
