The Vivado® , Xilinx SDK, or third-party tools can establish a JTAG connection to the XCVU37P FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the micro-USB connector (J2). Alternatively, a JTAG cable can be connected to the keyed flat cable header (J4). JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pins M[2:0], wired to SW1 positions [2:4].