The four connected GTY Quads on the left side of the XCVU37P FPGA are described in this section (MGTY235- MGTY228 are not used).
- Quad 227
- MGTREFCLK0 - PCIE_CLK2_P/N (U94)
- MGTREFCLK1 - not connected
- Four GTY transceivers allocated to PCIe lanes 3:0 PCIE_EP_TX/RX[3:0]
- Quad 226
- MGTREFCLK0 - not connected
- MGTREFCLK1 - not connected
- Four GTY transceivers allocated to PCIe lanes 7:4 PCIE_EP_TX/RX[7:4]
- Quad 225
- MGTREFCLK0 - PCIE_CLK1_P/N (U94)
- MGTREFCLK1 - not connected
- Four GTY transceivers allocated to PCIe lanes 11:8 PCIE_EP_TX/RX[11:8]
- Quad 224
- MGTREFCLK0 - not connected
- MGTREFCLK1 - not connected
- Four GTY transceivers allocated to PCIe lanes 15:12 PCIE_EP_TX/RX[15:12]
The XCVU37P left-side GTY transceiver interface assignments are shown in the following figure.
Figure 1. XCVU37P Left-side GTY Transceiver Assignments
