[Figure 1, callout 20]
The 16-lane PCI Express® edge connector P1 performs data transfers at the rate of 2.5 GT/s for Gen1 applications, 5.0 GT/s for Gen2 applications, 8.0 GT/s for Gen3 applications and 16.0 GT/s for Gen4 applications. The PCIe® transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair.
The XCVU37P-2FSVH2892E (-2 speed grade) is deployed on the VCU128 to support up to Gen4 x8. User selectable as PCIe Gen3 x16 or dual Gen4 x8. The PCIe reference clock is input from the P1 edge connector. The PCIe clock is routed from P1 pin A16 (P) and pin A17 (N) to a 1-to-2 ICS85411A clock buffer U94. The Q0 output of U94 is wired to the GTY225 MGTHREFCLK0 input (see Table 3). The Q1 output of U94 is wired to the GTY227 MGTHREFCLK0 input (see Table 1). PCIe lane width/size is selected by jumper J46. The default lane size selection is 16-lane (J46 pins 7 and 8 jumpered). The 1-to-2 U94 PCIe clock buffer circuit and J46 lane size jumper are shown in the following figure.
The tables in Left-side GTY Transceiver Connectivity list the PCIe P1 edge connector wiring to the XCVU37P FPGA U1 MGTY transceiver banks 227-224. The two PCIe P1 edge connector control signals PCIE_EP_WAKE (P1 pin B11) and PCIE_EP_PERST (P1 pin A11) are level-shifted by SN74AVC2T245 U70 and connected to the XCVU37P U1 bank 65 pin BJ42 and pin BF41, respectively. For additional information about UltraScale™ PCIe functionality, see the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156). Additional information about the PCI Express standard is available on the PCI Express standard website.