Programmable QSFP3 Clock

VCU128 Evaluation Board User Guide (UG1302)

Document ID
UG1302
Release Date
2022-05-06
Revision
1.2 English

[Figure 1, callout 15]

The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U82) connected to FPGA U1 GTY bank 132 MGTREFCLK0 P/N pins Y42 and Y43 (series capacitor coupled), respectively.

On power-up, the U82 SI570 user clock defaults to an output frequency of 156.250 MHz. The Zynq-7000 SoC system controller or FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the VCU128 evaluation board resets the QSFP3 clock to the default frequency of 156.250 MHz.

  • Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
  • Frequency tolerance: 50 ppm
  • 3.3V LVDS differential output

The programmable QSFP3 clock circuit is shown in the following figure.

Figure 1. QSFP3 Clock