[Figure 1, callout 6]
- Manufacturer: Cypress
- Part Number: CY7C4142KV13_106FCXC
- Description:
- 144-Mbit density (4M × 36)
- Dual independent 36-bit bidirectional double data rate (DDR) data ports
- Supports concurrent read/write transactions on both ports
- Single address port used to control both data ports
- 1.2V 361-ball FCBGA
- Maximum operating frequency of 1066 MHz
The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).
The 72-bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68, 69, and 70. The QDR4 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the INTERNAL VREF mode. The connections between the 72-bit interface QDR4 component memories and XCVU37P banks 68, 69, and 70 are listed in the following table.
FPGA (U1) Pin | Schematic Net Name | I/O Standard | Component Memory | |
---|---|---|---|---|
Pin # | Pin Name | |||
QDR4 A-side Data | ||||
BM14 | QDR4_DQA0 | C8 | DQA0 | |
BM13 | QDR4_DQA1 | B7 | DQA1 | |
BN15 | QDR4_DQA2 | C6 | DQA2 | |
BN12 | QDR4_DQA3 | D5 | DQA3 | |
BM15 | QDR4_DQA4 | D7 | DQA4 | |
BP13 | QDR4_DQA5 | A4 | DQA5 | |
BP14 | QDR4_DQA6 | F5 | DQA6 | |
BM12 | QDR4_DQA7 | A6 | DQA7 | |
BL15 | QDR4_DQA8 | A8 | DQA8 | |
BM9 | QDR4_DQA9 | H3 | DQA9 | |
BK9 | QDR4_DQA10 | H5 | DQA10 | |
BL10 | QDR4_DQA11 | J2 | DQA11 | |
BK10 | QDR4_DQA12 | J4 | DQA12 | |
BL8 | QDR4_DQA13 | B2 | DQA13 | |
BN10 | QDR4_DQA14 | E2 | DQA14 | |
BM10 | QDR4_DQA15 | G2 | DQA15 | |
BN9 | QDR4_DQA16 | G4 | DQA16 | |
BJ9 | QDR4_DQA17 | B5 | DQA17 | |
BL12 | QDR4_DQA18 | C12 | DQA18 | |
BK14 | QDR4_DQA19 | B13 | DQA19 | |
BJ12 | QDR4_DQA20 | C14 | DQA20 | |
BK15 | QDR4_DQA21 | D15 | DQA21 | |
BL13 | QDR4_DQA22 | D13 | DQA22 | |
BH14 | QDR4_DQA23 | A16 | DQA23 | |
BH15 | QDR4_DQA24 | F15 | DQA24 | |
BJ14 | QDR4_DQA25 | A14 | DQA25 | |
BJ13 | QDR4_DQA26 | A12 | DQA26 | |
BE9 | QDR4_DQA27 | H17 | DQA27 | |
BE10 | QDR4_DQA28 | H15 | DQA28 | |
BG13 | QDR4_DQA29 | J18 | DQA29 | |
BE11 | QDR4_DQA30 | J16 | DQA30 | |
BF10 | QDR4_DQA31 | B18 | DQA31 | |
BG12 | QDR4_DQA32 | E18 | DQA32 | |
BG9 | QDR4_DQA33 | G18 | DQA33 | |
BG10 | QDR4_DQA34 | G16 | DQA34 | |
BF12 | QDR4_DQA35 | B15 | DQA35 | |
QDR4 A-side Control | ||||
BP12 | QDR4_DKA0_P | F4 | DKA0_P | |
BP11 | QDR4_DKA0_N | F3 | DKA0_N | |
BH10 | QDR4_DKA1_P | F16 | DKA1_P | |
BH9 | QDR4_DKA1_N | F17 | DKA1_N | |
BP9 | QDR4_QKA0_P | C4 | QKA0_P | |
BP8 | QDR4_QKA0_N | D3 | QKA0_N | |
BJ11 | QDR4_QKA1_P | C16 | QKA1_P | |
BK11 | QDR4_QKA1_N | D17 | QKA1_N | |
BM8 | QDR4_QVLDA0 | C3 | QVLDA0 | |
BK13 | QDR4_QVLDA1 | C17 | QVLDA1 | |
BM3 | QDR4_LDA_N | H8 | LDA_N | |
BM4 | QDR4_RWA_N | H10 | RWA_N | |
R522(GND) 1 | QDR4_DINVA0 | D8 | DINVA0 | |
R519(GND) 1 | QDR4_DINVA1 | D12 | DINVA1 | |
QDR4 B-side Data | ||||
H15 | QDR4_DQB0 | U8 | DQB0 | |
J15 | QDR4_DQB1 | V7 | DQB1 | |
J12 | QDR4_DQB2 | U6 | DQB2 | |
J11 | QDR4_DQB3 | T5 | DQB3 | |
H14 | QDR4_DQB4 | T7 | DQB4 | |
G13 | QDR4_DQB5 | W4 | DQB5 | |
J14 | QDR4_DQB6 | P5 | DQB6 | |
H12 | QDR4_DQB7 | W6 | DQB7 | |
H13 | QDR4_DQB8 | W8 | DQB8 | |
G11 | QDR4_DQB9 | M3 | DQB9 | |
E12 | QDR4_DQB10 | M5 | DQB10 | |
F10 | QDR4_DQB11 | L2 | DQB11 | |
E11 | QDR4_DQB12 | L4 | DQB12 | |
D10 | QDR4_DQB13 | V2 | DQB13 | |
E9 | QDR4_DQB14 | R2 | DQB14 | |
F9 | QDR4_DQB15 | N2 | DQB15 | |
F11 | QDR4_DQB16 | N4 | DQB16 | |
D11 | QDR4_DQB17 | V5 | DQB17 | |
E14 | QDR4_DQB18 | U12 | DQB18 | |
A14 | QDR4_DQB19 | V13 | DQB19 | |
D15 | QDR4_DQB20 | U14 | DQB20 | |
B15 | QDR4_DQB21 | T15 | DQB21 | |
F13 | QDR4_DQB22 | T13 | DQB22 | |
C15 | QDR4_DQB23 | W16 | DQB23 | |
F15 | QDR4_DQB24 | P15 | DQB24 | |
A15 | QDR4_DQB25 | W14 | DQB25 | |
F14 | QDR4_DQB26 | W12 | DQB26 | |
C12 | QDR4_DQB27 | M17 | DQB27 | |
A11 | QDR4_DQB28 | M15 | DQB28 | |
B13 | QDR4_DQB29 | L18 | DQB29 | |
B12 | QDR4_DQB30 | L16 | DQB30 | |
A8 | QDR4_DQB31 | V18 | DQB31 | |
A9 | QDR4_DQB32 | R18 | DQB32 | |
B11 | QDR4_DQB33 | N18 | DQB33 | |
B10 | QDR4_DQB34 | N16 | DQB34 | |
A10 | QDR4_DQB35 | V15 | DQB35 | |
QDR4 B-side Control | ||||
K14 | QDR4_DKB0_P | P4 | DKB0_P | |
K13 | QDR4_DKB0_N | P3 | DKB0_N | |
C10 | QDR4_DKB1_P | P16 | DKB1_P | |
C9 | QDR4_DKB1_N | P17 | DKB1_N | |
H10 | QDR4_QKB0_P | U4 | QKB0_P | |
G10 | QDR4_QKB0_N | T3 | QKB0_N | |
E13 | QDR4_QKB1_P | U16 | QKB1_P | |
D12 | QDR4_QKB1_N | T17 | QKB1_N | |
D9 | QDR4_QVLDB0 | U3 | QVLDB0 | |
D14 | QDR4_QVLDB1 | U17 | QVLDB1 | |
BL2 | QDR4_LDB_N | H12 | LDB_N | |
BL3 | QDR4_RWB_N | L10 | RWB_N | |
R606(GND) 1 | QDR4_DINVB0 | T8 | DINVB0 | |
R602(GND) 1 | QDR4_DINVB1 | T12 | DINVB1 | |
Common | ||||
BF5 | QDR4_A0 | F10 | A0 | |
BF1 | QDR4_A1 | G10 | A1 | |
BE1 | QDR4_A2 | N10 | A2 | |
BE3 | QDR4_A3 | G7 | A3 | |
BE4 | QDR4_A4 | G13 | A4 | |
BE5 | QDR4_A5 | J7 | A5 | |
BE6 | QDR4_A6 | J13 | A6 | |
BF2 | QDR4_A7 | L7 | A7 | |
BF3 | QDR4_A8 | L13 | A8 | |
BG2 | QDR4_A9 | N7 | A9 | |
BG3 | QDR4_A10 | N13 | A10 | |
BG4 | QDR4_A11 | M8 | A11 | |
BG5 | QDR4_A12 | M12 | A12 | |
BF7 | QDR4_A13 | F8 | A13 | |
BF8 | QDR4_A14 | F12 | A14 | |
BG7 | QDR4_A15 | P8 | A15 | |
BG8 | QDR4_A16 | P12 | A16 | |
BJ7 | QDR4_A17 | L9 | A17 | |
BH7 | QDR4_A18 | L11 | A18_36M | |
BK8 | QDR4_A19 | J9 | A19_72M | |
BJ8 | QDR4_A20 | J11 | A20_144M | |
BJ6 | QDR4_A21 | G9 | A21_288M | |
BK5 | QDR4_A22 | G11 | A22_576M | |
BH6 | QDR4_A23 | N9 | A23_1152M | |
BK4 | QDR4_A24 | N11 | A24_2304M | |
BK6 | QDR4_AP | P10 | AP | |
BJ1 | QDR4_AINV | M10 | AINV | |
BH5 | QDR4_CK_P | J10 | CK_P | |
BH4 | QDR4_CK_N | K10 | CK_N | |
BJ3 | QDR4_LBK0_N | A10 | LBK0_N | |
BH1 | QDR4_LBK1_N | B10 | LBK1_N | |
BH2 | QDR4_CFG_N | D10 | CFG_N | |
BJ2 | QDR4_PE_N | V10 | PE_N | |
BK1 | QDR4_RST_N | K18 | RST_N | |
QDR4 U40 ZQ_ZT pin W10 is wired to 220Ω R604 to GND | ||||
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The VCU128 QDR-IV dual independent 36-bit bidirectional data port memory component interfaces adhere to the constraints guidelines documented in the "QDR-IV Design Guidelines" section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 QDR-IV memory component interface is a 40Ω impedance implementation.
For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", “VREF”, and “Internal VREF” sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Cypress QDR-IV component memory, see the Cypress CY7C4142KV13_106FCXC Data Sheet at the Cypress Semiconductor website.