[Figure 1, callout 12]
The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U96) connected to FPGA U1 HP bank 69 QDR4 interface GC pins BJ4 (P) and BK3 (N) and is series capacitor coupled.
- Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz)
- 0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
- 3.3V LVDS differential output
The QDR4 interface fixed frequency clock circuit is shown in the following figure.
Figure 1. QDR4 Interface Clock
