QSFP28 Connections to Transceiver Banks 67 and 69

VCU128 Evaluation Board User Guide (UG1302)
Document ID
UG1302
Release Date
2022-05-06
Revision
1.2 English

The following table lists the QSFP28 module level-shifted control signal connections to XCVU37P FPGA U1 bank 67 (QSFP1, QSFP4) and bank 69 (QSFP2, QSFP3).

Table 1. XCVU37P U1 to QSFP28 Module Control and I2C Connections
FPGA (U1) Pin Schematic Net Name 1 , 2 FPGA (U1) Direction Module Pin Num Module Pin Name
QSFP1 J42 (U1 bank 67)
BM24 QSFP1_MODSKLL_LS Output 8 MODSELL
BN25 QSFP1_RESETL_LS Output 9 RESETL
BM25 QSFP1_MODPRSL_LS Output 27 MODPRSL
BP24 QSFP1_INTL_LS Input 28 INTL
BN24 QSFP1_LPMODE_LS Output 31 LPMODE
U54.13 QSFP1_I2C_SDA BiDir 12 SDA
U54.14 QSFP1_I2C_SCL Output 11 SCL
QSFP2 J39 (U1 bank 69)
BN5 QSFP2_MODSKLL_LS Output 8 MODSELL
BN6 QSFP2_RESETL_LS Output 9 RESETL
BN7 QSFP2_MODPRSL_LS Output 27 MODPRSL
BP6 QSFP2_INTL_LS Input 28 INTL
BP7 QSFP2_LPMODE_LS Output 31 LPMODE
U54.15 QSFP2_I2C_SDA BiDir 12 SDA
U54.16 QSFP2_I2C_SCL Output 11 SCL
QSFP3 J35 (U1 bank 69)
BM5 QSFP3_MODSKLL_LS Output 8 MODSELL
BL6 QSFP3_RESETL_LS Output 9 RESETL
BM7 QSFP3_MODPRSL_LS Output 27 MODPRSL
BL7 QSFP3_INTL_LS Input 28 INTL
BN4 QSFP3_LPMODE_LS Output 31 LPMODE
U54.17 QSFP3_I2C_SDA BiDir 12 SDA
U54.18 QSFP3_I2C_SCL Output 11 SCL
QSFP4 J32 (U1 bank 67)
BK23 QSFP4_MODSKLL_LS Output 8 MODSELL
BK24 QSFP4_RESETL_LS Output 9 RESETL
BL22 QSFP4_MODPRSL_LS Output 27 MODPRSL
BH21 QSFP4_INTL_LS Input 28 INTL
BH21 QSFP4_LPMODE_LS Output 31 LPMODE
U54.19 QSFP4_I2C_SDA BiDir 12 SDA
U54.20 QSFP4_I2C_SCL Output 11 SCL
  1. The QSFP28 connector control signals are level-shifted.
  2. The four QSFP28 connector I2C SCL/SDA signals are connected via I2C switch U54 to the I2C1_SCL/SDA bus. See I2C Bus, Topology, and Switches section.

For additional information about the quad small form factor pluggable (28 Gb/s QSFP28) module, see the SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ on the SNIA Technology Affiliates website.