RLD3 Component Memory

[Figure 1, callout 5]

The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit 1.125 Gb RLDRAM3 devices located at U39 and U37.

• Manufacturer: Micron
• Part Number: MT44K32M36RB-107E
• Description:
  • 1.125 Gb (32 Mb x 36)
  • 1.2V 168-ball BGA
  • Up to RL3-1866

The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).

This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V VTT termination voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The connections between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are listed in the following table.

The VCU128 RLD3 72-bit memory component interface adheres to the constraints guidelines documented in the "RLD3 Design Guidelines" section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150). The VCU128 RLD3 memory component interface is a 40Ω impedance implementation.

For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", “VREF”, and “Internal VREF” sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron RLD3 component memory, see the Micron MT44K32M36RB Data Sheet at the Micron Technology website.