The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/06/2022 Version 1.2 | |
| Table 1 | Added HBM reference clock option. |
| I/O Voltage Rails | Updated to include HBM banks. |
| Right-side Quads | Updated GTY quad information. |
| PCI Express Endpoint Connectivity | Updated the reference to the FPGA. |
| Table 1 | Updated pin assignment, I/O standard, and net names as needed. |
| FMCP Connector J18 | Updated pin assignment and static net name. |
| 04/21/2021 Version 1.1 | |
| Board Power System | Revised the Renesas smart power stage module part number in the power system block diagram. |
| 12/21/2018 Version 1.0 | |
| Initial release. | N/A |