Right-side GTY Transceiver Connectivity

VCU128 Evaluation Board User Guide (UG1302)
Document ID
UG1302
Release Date
2022-05-06
Revision
1.2 English

The following tables list the connectivity of the ten XCVU37P FPGA U1 right-side GTY transceivers.

Table 1. XCVU37P U1 GTY Transceiver Bank 135 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 135 G48 MGTYTXP0_135 QSFP1_TX1_P 36 TX1P QSFP1 J42
G49 MGTYTXN0_135 QSFP1_TX1_N 37 TX1N
G53 MGTYRXP0_135 QSFP1_RX1_P 17 RX1P
G54 MGTYRXN0_135 QSFP1_RX1_N 18 RX1N
E48 MGTYTXP1_135 QSFP1_TX2_P 3 TX2P
E49 MGTYTXN1_135 QSFP1_TX2_N 2 TX2N
F51 MGTYRXP1_135 QSFP1_RX2_P 22 RX2P
F52 MGTYRXN1_135 QSFP1_RX2_N 21 RX2N
C48 MGTYTXP2_135 QSFP1_TX3_P 33 TX3P
C49 MGTYTXN2_135 QSFP1_TX3_N 34 TX3N
E53 MGTYRXP2_135 QSFP1_RX3_P 14 RX3P
E54 MGTYRXN2_135 QSFP1_RX3_N 15 RX3N
A49 MGTYTXP3_135 QSFP1_TX4_P 6 TX4P
A50 MGTYTXN3_135 QSFP1_TX4_N 5 TX4N
D51 MGTYRXP3_135 QSFP1_RX4_P 25 RX4P
D52 MGTYRXN3_135 QSFP1_RX4_N 24 RX4N
P42 MGTREFCLK0P_135 QSFP_SI570_CLOCK_P 1 4 OUT U95 SI570 I2C prog. osc.
P43 MGTREFCLK0N_135 QSFP_SI570_CLOCK_N 1 5 OUT_B
M42 MGTREFCLK1P_135 NC NC NC NC
M43 MGTREFCLK1N_135
  1. Series 0.01 µF capacitor coupled.
Table 2. XCVU37P U1 GTY Transceiver Bank 134 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 134 L48 MGTYTXP0_134 QSFP2_TX1_P 36 TX1P  
L49 MGTYTXN0_134 QSFP2_TX1_N 37 TX1N
L53 MGTYRXP0_134 QSFP2_RX1_P 17 RX1P
L54 MGTYRXN0_134 QSFP2_RX1_N 18 RX1N
L44 MGTYTXP1_134 QSFP2_TX2_P 3 TX2P
L45 MGTYTXN1_134 QSFP2_TX2_N 2 TX2N
K51 MGTYRXP1_134 QSFP2_RX2_P 22 RX2P
K52 MGTYRXN1_134 QSFP2_RX2_N 21 RX2N
K46 MGTYTXP2_134 QSFP2_TX3_P 33 TX3P
K47 MGTYTXN2_134 QSFP2_TX3_N 34 TX3N
J53 MGTYRXP2_134 QSFP2_RX3_P 14 RX3P
J54 MGTYRXN2_134 QSFP2_RX3_N 15 RX3N
J48 MGTYTXP3_134 QSFP2_TX4_P 6 TX4P
J49 MGTYTXN3_134 QSFP2_TX4_N 5 TX4N
H51 MGTYRXP3_134 QSFP2_RX4_P 25 RX4P
H52 MGTYRXN3_134 QSFP2_RX4_N 24 RX4N
T42 MGTREFCLK0P_134 QSFP2_SI570_CLOCK_P 1 4 OUT U90 SI570 I2C prog. osc.
T43 MGTREFCLK0N_134 QSFP2_SI570_CLOCK_N 1 5 OUT_B
R40 MGTREFCLK1P_134 SI5328_CLOCK1_C_P 1 28 CKOUT1_P U87 SI5328B jitter atten.
R41 MGTREFCLK1N_134 SI5328_CLOCK1_C_N 1 29 CKOUT1_N
  1. Series 0.01 µF capacitor coupled.
Table 3. XCVU37P U1 GTY Transceiver Bank 132 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 132 V46 MGTYTXP0_132 QSFP3_TX1_P 36 TX1P QSFP2 J35
V47 MGTYTXN0_132 QSFP3_TX1_N 37 TX1N
U53 MGTYRXP0_132 QSFP3_RX1_P 17 RX1P
U54 MGTYRXN0_132 QSFP3_RX1_N 18 RX1N
U44 MGTYTXP1_132 QSFP3_TX2_P 3 TX2P
U45 MGTYTXN1_132 QSFP3_TX2_N 2 TX2N
U49 MGTYRXP1_132 QSFP3_RX2_P 22 RX2P
U50 MGTYRXN1_132 QSFP3_RX2_N 21 RX2N
T46 MGTYTXP2_132 QSFP3_TX3_P 33 TX3P
T47 MGTYTXN2_132 QSFP3_TX3_N 34 TX3N
T51 MGTYRXP2_132 QSFP3_RX3_P 14 RX3P
T52 MGTYRXN2_132 QSFP3_RX3_N 15 RX3N
R44 MGTYTXP3_132 QSFP3_TX4_P 6 TX4P
R45 MGTYTXN3_132 QSFP3_TX4_N 5 TX4N
R53 MGTYRXP3_132 QSFP3_RX4_P 25 RX4P
R54 MGTYRXN3_132 QSFP3_RX4_N 24 RX4N
Y42 MGTREFCLK0P_132 QSFP3_SI570_CLOCK_P 1 4 OUT U82 SI570 I2C prog. osc.
Y43 MGTREFCLK0N_132 QSFP3_SI570_CLOCK_N 1 5 OUT_B
W40 MGTREFCLK1P_132 SI5328_CLOCK2_C_P 1 35 CKOUT2_P U87 SI5328B jitter atten.
W41 MGTREFCLK1N_132 SI5328_CLOCK2_C_N 1 34 CKOUT2_N
  1. Series 0.01 µF capacitor coupled.
Table 4. XCVU37P U1 GTY Transceiver Bank 131 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 131 AA44 MGTYTXP0_131 QSFP4_TX1_P 36 TX1P QSFP2 J32
AA45 MGTYTXN0_131 QSFP4_TX1_N 37 TX1N
AA53 MGTYRXP0_131 QSFP4_RX1_P 17 RX1P
AA54 MGTYRXN0_131 QSFP4_RX1_N 18 RX1N
Y46 MGTYTXP1_131 QSFP4_TX2_P 3 TX2P
Y47 MGTYTXN1_131 QSFP4_TX2_N 2 TX2N
Y51 MGTYRXP1_131 QSFP4_RX2_P 22 RX2P
Y52 MGTYRXN1_131 QSFP4_RX2_N 21 RX2N
W48 MGTYTXP2_131 QSFP4_TX3_P 33 TX3P
W49 MGTYTXN2_131 QSFP4_TX3_N 34 TX3N
W53 MGTYRXP2_131 QSFP4_RX3_P 14 RX3P
W54 MGTYRXN2_131 QSFP4_RX3_N 15 RX3N
W44 MGTYTXP3_131 QSFP4_TX4_P 6 TX4P
W45 MGTYTXN3_131 QSFP4_TX4_N 5 TX4N
V51 MGTYRXP3_131 QSFP4_RX4_P 25 RX4P
V52 MGTYRXN3_131 QSFP4_RX4_N 24 RX4N
AB42 MGTREFCLK0P_131 QSFP4_SI570_CLOCK_P 1 4 OUT U80 SI570 I2C prog. osc.
AB43 MGTREFCLK0N_131 QSFP4_SI570_CLOCK_N 1 5 OUT_B
AA40 MGTREFCLK1P_131 SMA_REFCLK_INPUT_P 1 1 SIG SMA J24 (P) SMA J26 (N)
AA41 MGTREFCLK1N_131 SMA_REFCLK_INPUT_N 1 1 SIG
  1. Series 0.01 µF capacitor coupled.
Table 5. XCVU37P U1 GTY Transceiver Bank 129 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 129 AG48 MGTYTXP0_129 FMCP_HSPC_DP20_C2M_P Z8 DP20_C2M_P FMCP HSPC J18
AG49 MGTYTXN0_129 FMCP_HSPC_DP20_C2M_N Z9 DP20_C2M_N
AG53 MGTYRXP0_129 FMCP_HSPC_DP20_M2C_P M14 DP20_M2C_P
AG54 MGTYRXN0_129 FMCP_HSPC_DP20_M2C_N M15 DP20_M2C_N
AG44 MGTYTXP1_129 FMCP_HSPC_DP21_C2M_P Y6 DP21_C2M_P
AG45 MGTYTXN1_129 FMCP_HSPC_DP21_C2M_N Y7 DP21_C2M_N
AF51 MGTYRXP1_129 FMCP_HSPC_DP21_M2C_P M10 DP21_M2C_P
AF52 MGTYRXN1_129 FMCP_HSPC_DP21_M2C_N M11 DP21_M2C_N
AF46 MGTYTXP2_129 FMCP_HSPC_DP22_C2M_P Z4 DP22_C2M_P
AF47 MGTYTXN2_129 FMCP_HSPC_DP22_C2M_N Z5 DP22_C2M_N
AE53 MGTYRXP2_129 FMCP_HSPC_DP22_M2C_P M6 DP22_M2C_P
AE54 MGTYRXN2_129 FMCP_HSPC_DP22_M2C_N M7 DP22_M2C_N
AE44 MGTYTXP3_129 FMCP_HSPC_DP23_C2M_P Y2 DP23_C2M_P
AE45 MGTYTXN3_129 FMCP_HSPC_DP23_C2M_N Y3 DP23_C2M_N
AE49 MGTYRXP3_129 FMCP_HSPC_DP23_M2C_P M2 DP23_M2C_P
AE50 MGTYRXN3_129 FMCP_HSPC_DP23_M2C_N M3 DP23_M2C_N
AG40 MGTREFCLK0P_129 FMCP_HSPC_GBTCLK5_M2C_P 1 Z20 GBTCLK5_M2C_P
AG41 MGTREFCLK0N_129 FMCP_HSPC_GBTCLK5_M2C_N 1 Z21 GBTCLK5_M2C_N
AF42 MGTREFCLK1P_129 NC NC NC NC
AF43 MGTREFCLK1N_129
  1. Series 0.01 µF capacitor coupled.
Table 6. XCVU37P U1 GTY Transceiver Bank 128 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 128 AK46 MGTYTXP0_128 FMCP_HSPC_DP16_C2M_P M26 DP16_C2M_P FMCP HSPC J18
AK47 MGTYTXN0_128 FMCP_HSPC_DP16_C2M_N M27 DP16_C2M_N
AL49 MGTYRXP0_128 FMCP_HSPC_DP16_M2C_P Z32 DP16_M2C_P
AL50 MGTYRXN0_128 FMCP_HSPC_DP16_M2C_N Z33 DP16_M2C_N
AJ48 MGTYTXP1_128 FMCP_HSPC_DP17_C2M_P M30 DP17_C2M_P
AJ49 MGTYTXN1_128 FMCP_HSPC_DP17_C2M_N M31 DP17_C2M_N
AK51 MGTYRXP1_128 FMCP_HSPC_DP17_M2C_P Y34 DP17_M2C_P
AK52 MGTYRXN1_128 FMCP_HSPC_DP17_M2C_N Y35 DP17_M2C_N
AJ44 MGTYTXP2_128 FMCP_HSPC_DP18_C2M_P M34 DP18_C2M_P
AJ45 MGTYTXN2_128 FMCP_HSPC_DP18_C2M_N M35 DP18_C2M_N
AJ53 MGTYRXP2_128 FMCP_HSPC_DP18_M2C_P Z36 DP18_M2C_P
AJ54 MGTYRXN2_128 FMCP_HSPC_DP18_M2C_N Z37 DP18_M2C_N
AH46 MGTYTXP3_128 FMCP_HSPC_DP19_C2M_P M38 DP19_C2M_P
AH47 MGTYTXN3_128 FMCP_HSPC_DP19_C2M_N M39 DP19_C2M_N
AH51 MGTYRXP3_128 FMCP_HSPC_DP19_M2C_P Y38 DP19_M2C_P
AH52 MGTYRXN3_128 FMCP_HSPC_DP19_M2C_N Y39 DP19_M2C_N
AJ40 MGTREFCLK0P_128 FMCP_HSPC_GBTCLK4_M2C_P 1 L4 GBTCLK4_M2C_P
AJ41 MGTREFCLK0N_128 FMCP_HSPC_GBTCLK4_M2C_N 1 L5 GBTCLK4_M2C_N
AH42 MGTREFCLK1P_128 NC NC NC NC
AH43 MGTREFCLK1N_128
  1. Series 0.01 µF capacitor coupled.
Table 7. XCVU37P U1 GTY Transceiver Bank 127 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 127 AP46 MGTYTXP0_127 FMCP_HSPC_DP12_C2M_P Z28 DP12_C2M_P FMCP HSPC J18
AP47 MGTYTXN0_127 FMCP_HSPC_DP12_C2M_N Z29 DP12_C2M_N
AN53 MGTYRXP0_127 FMCP_HSPC_DP12_M2C_P Y14 DP12_M2C_P
AN54 MGTYRXN0_127 FMCP_HSPC_DP12_M2C_N Y15 DP12_M2C_N
AN44 MGTYTXP1_127 FMCP_HSPC_DP13_C2M_P Y30 DP13_C2M_P
AN45 MGTYTXN1_127 FMCP_HSPC_DP13_C2M_N Y31 DP13_C2M_N
AN49 MGTYRXP1_127 FMCP_HSPC_DP13_M2C_P Z16 DP13_M2C_P
AN50 MGTYRXN1_127 FMCP_HSPC_DP13_M2C_N Z17 DP13_M2C_N
AM46 MGTYTXP2_127 FMCP_HSPC_DP14_C2M_P M18 DP14_C2M_P
AM47 MGTYTXN2_127 FMCP_HSPC_DP14_C2M_N M19 DP14_C2M_N
AM51 MGTYRXP2_127 FMCP_HSPC_DP14_M2C_P Y18 DP14_M2C_P
AM52 MGTYRXN2_127 FMCP_HSPC_DP14_M2C_N Y19 DP14_M2C_N
AL44 MGTYTXP3_127 FMCP_HSPC_DP15_C2M_P M22 DP15_C2M_P
AL45 MGTYTXN3_127 FMCP_HSPC_DP15_C2M_N M23 DP15_C2M_N
AL53 MGTYRXP3_127 FMCP_HSPC_DP15_M2C_P Y22 DP15_M2C_P
AL54 MGTYRXN3_127 FMCP_HSPC_DP15_M2C_N Y23 DP15_M2C_N
AL40 MGTREFCLK0P_127 FMCP_HSPC_GBTCLK3_M2C_P 1 L8 GBTCLK3_M2C_P
AL41 MGTREFCLK0N_127 FMCP_HSPC_GBTCLK3_M2C_N 1 L9 GBTCLK3_M2C_N
AK42 MGTREFCLK1P_127 NC NC NC NC
AK43 MGTREFCLK1N_127
  1. Series 0.01 µF capacitor coupled.
Table 8. XCVU37P U1 GTY Transceiver Bank 126 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 126 AU48 MGTYTXP0_126 FMCP_HSPC_DP8_C2M_P B28 DP8_C2M_P FMCP HSPC J18
AU49 MGTYTXN0_126 FMCP_HSPC_DP8_C2M_N B29 DP8_C2M_N
AU53 MGTYRXP0_126 FMCP_HSPC_DP8_M2C_P B8 DP8_M2C_P
AU54 MGTYRXN0_126 FMCP_HSPC_DP8_M2C_N B9 DP8_M2C_N
AT46 MGTYTXP1_126 FMCP_HSPC_DP9_C2M_P B24 DP9_C2M_P
AT47 MGTYTXN1_126 FMCP_HSPC_DP9_C2M_N B25 DP9_C2M_N
AT51 MGTYRXP1_126 FMCP_HSPC_DP9_M2C_P B4 DP9_M2C_P
AT52 MGTYRXN1_126 FMCP_HSPC_DP9_M2C_N B5 DP9_M2C_N
AR48 MGTYTXP2_126 FMCP_HSPC_DP10_C2M_P Z24 DP10_C2M_P
AR49 MGTYTXN2_126 FMCP_HSPC_DP10_C2M_N Z25 DP10_C2M_N
AR53 MGTYRXP2_126 FMCP_HSPC_DP10_M2C_P Y10 DP10_M2C_P
AR54 MGTYRXN2_126 FMCP_HSPC_DP10_M2C_N Y11 DP10_M2C_N
AR44 MGTYTXP3_126 FMCP_HSPC_DP11_C2M_P Y26 DP11_C2M_P
AR45 MGTYTXN3_126 FMCP_HSPC_DP11_C2M_N Y27 DP11_C2M_N
AP51 MGTYRXP3_126 FMCP_HSPC_DP11_M2C_P Z12 DP11_M2C_P
AP52 MGTYRXN3_126 FMCP_HSPC_DP11_M2C_N Z13 DP11_M2C_N
AN40 MGTREFCLK0P_126 FMCP_HSPC_GBTCLK2_M2C_P 1 L12 GBTCLK2_M2C_P
AN41 MGTREFCLK0N_126 FMCP_HSPC_GBTCLK2_M2C_N1 L13 GBTCLK2_M2C_N
AM42 MGTREFCLK1P_126 NC NC NC NC
AM43 MGTREFCLK1N_126
  1. Series 0.01 µF capacitor coupled.
Table 9. XCVU37P U1 GTY Transceiver Bank 125 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY bank 125 AY46 MGTYTXP0_125 FMCP_HSPC_DP4_C2M_P A34 DP4_C2M_P FMCP HSPC J18
AY47 MGTYTXN0_125 FMCP_HSPC_DP4_C2M_N A35 DP4_C2M_N
AY51 MGTYRXP0_125 FMCP_HSPC_DP4_M2C_P A14 DP4_M2C_P
AY52 MGTYRXN0_125 FMCP_HSPC_DP4_M2C_N A15 DP4_M2C_N
AW44 MGTYTXP1_125 FMCP_HSPC_DP5_C2M_P A38 DP5_C2M_P
AW45 MGTYTXN1_125 FMCP_HSPC_DP5_C2M_N A39 DP5_C2M_N
AW53 MGTYRXP1_125 FMCP_HSPC_DP5_M2C_P A18 DP5_M2C_P
AW54 MGTYRXN1_125 FMCP_HSPC_DP5_M2C_N A19 DP5_M2C_N
AV46 MGTYTXP2_125 FMCP_HSPC_DP6_C2M_P B36 DP6_C2M_P
AV47 MGTYTXN2_125 FMCP_HSPC_DP6_C2M_N B37 DP6_C2M_N
AW49 MGTYRXP2_125 FMCP_HSPC_DP6_M2C_P B16 DP6_M2C_P
AW50 MGTYRXN2_125 FMCP_HSPC_DP6_M2C_N B17 DP6_M2C_N
AU44 MGTYTXP3_125 FMCP_HSPC_DP7_C2M_P B32 DP7_C2M_P
AU45 MGTYTXN3_125 FMCP_HSPC_DP7_C2M_N B33 DP7_C2M_N
AV51 MGTYRXP3_125 FMCP_HSPC_DP7_M2C_P B12 DP7_M2C_P
AV52 MGTYRXN3_125 FMCP_HSPC_DP7_M2C_N B13 DP7_M2C_N
AR40 MGTREFCLK0P_125 FMCP_HSPC_GBTCLK1_M2C_P 1 B20 GBTCLK1_M2C_P
AR41 MGTREFCLK0N_125 FMCP_HSPC_GBTCLK1_M2C_N 1 B21 GBTCLK1_M2C_N
AP42 MGTREFCLK1P_125 NC NC NC NC
AP43 MGTREFCLK1N_125
  1. Series 0.01 µF capacitor coupled.
Table 10. XCVU37P U1 GTY Transceiver Bank 124 Connections
MGT Bank FPGA (U1) Pin FPGA (U1) Pin Name Schematic Net Name Connected Pin Connected Pin Name Connected Device
GTY Bank 124 BC48 MGTYTXP0_124 FMCP_HSPC_DP0_C2M_P C2 DP0_C2M_P FMCP HSPC J18
BC49 MGTYTXN0_124 FMCP_HSPC_DP0_C2M_N C3 DP0_C2M_N
BC53 MGTYRXP0_124 FMCP_HSPC_DP0_M2C_P C6 DP0_M2C_P
BC54 MGTYRXN0_124 FMCP_HSPC_DP0_M2C_N C7 DP0_M2C_N
BC44 MGTYTXP1_124 FMCP_HSPC_DP1_C2M_P A22 DP1_C2M_P
BC45 MGTYTXN1_124 FMCP_HSPC_DP1_C2M_N A23 DP1_C2M_N
BB51 MGTYRXP1_124 FMCP_HSPC_DP1_M2C_P A2 DP1_M2C_P
BB52 MGTYRXN1_124 FMCP_HSPC_DP1_M2C_N A3 DP1_M2C_N
BB46 MGTYTXP2_124 FMCP_HSPC_DP2_C2M_P A26 DP2_C2M_P
BB47 MGTYTXN2_124 FMCP_HSPC_DP2_C2M_N A27 DP2_C2M_N
BA53 MGTYRXP2_124 FMCP_HSPC_DP2_M2C_P A6 DP2_M2C_P
BA54 MGTYRXN2_124 FMCP_HSPC_DP2_M2C_N A7 DP2_M2C_N
BA44 MGTYTXP3_124 FMCP_HSPC_DP3_C2M_P A30 DP3_C2M_P
BA45 MGTYTXN3_124 FMCP_HSPC_DP3_C2M_N A31 DP3_C2M_N
BA49 MGTYRXP3_124 FMCP_HSPC_DP3_M2C_P A10 DP3_M2C_P
BA50 MGTYRXN3_124 FMCP_HSPC_DP3_M2C_N A11 DP3_M2C_N
AV42 MGTREFCLK0P_124 FMCP_HSPC_GBTCLK0_M2C_P 1 D4 GBTCLK0_M2C_P
AV43 MGTREFCLK0N_124 FMCP_HSPC_GBTCLK0_M2C_N 1 D5 GBTCLK0_M2C_N
AT42 MGTREFCLK1P_124 NC NC NC NC
AT43 MGTREFCLK1N_124
  1. Series 0.01 µF capacitor coupled.