The ten connected GTY Quads on the right side of the XCVU37P FPGA are described in this section (MGTY133 and MGTY130 are not used).
Quad 135
- MGTREFCLK0 – QSFP1_SI570_CLOCK_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to QSFP1_TX/RX[1:4]_P/N
Quad 134
- MGTREFCLK0 – QSFP2_SI570_CLOCK_P/N
- MGTREFCLK1 – SI5328_CLOCK1_C_P/N
- Four GTY transceivers allocated to QSFP2_TX/RX[1:4]_P/N
Quad 132
- MGTREFCLK0 – QSFP3_SI570_CLOCK_P/N
- MGTREFCLK1 – SI5328_CLOCK2_C_P/N
- Four GTY transceivers allocated to QSFP3_TX/RX[1:4]_P/N
Quad 131
- MGTREFCLK0 – QSFP4_SI570_CLOCK_P/N
- MGTREFCLK1 – SMA_REFCLK_INPUT_P/N
- Four GTY transceivers allocated to QSFP4_TX/RX[1:4]_P/N
Quad 129
- MGTREFCLK0 - FMCP_HSPC_GBTCLK5_M2C_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to FMCP_HSPC_DP[20:23]
Quad 128
- MGTREFCLK0 - FMCP_HSPC_GBTCLK4_M2C_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to FMCP_HSPC_DP[16:19]
Quad 127
- MGTREFCLK0 – FMCP_HSPC_GBTCLK3_M2C_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to FMCP_HSPC_DP[12:15]
Quad 126
- MGTREFCLK0 – FMCP_HSPC_GBTCLK2_M2C_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to FMCP_HSPC_DP[8:11]
Quad 125
- MGTREFCLK0 – FMCP_HSPC_GBTCLK1_M2C_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to FMCP_HSPC_DP[4:7]
Quad 124
- MGTREFCLK0 – FMCP_HSPC_GBTCLK0_M2C_P/N
- MGTREFCLK1 – NC
- Four GTY transceivers allocated to FMCP_HSPC_DP[0:3]
The XCVU37P right-side GTY transceiver interface assignments are shown in the following figure.
Figure 1. XCVU37P Right-side GTY Transceiver Assignments
