[Figure 1, callout 27]
The VCU128 board provides a pair of SMAs for differential user clock I/O on FPGA U1 HP bank 67. The P-side SMA J12 net SMA_CLK_OUTPUT_P is connected to FPGA U1 HP bank 67 QBC pin BK26. The N-side SMA J13 net SMA_CLK_OUTPUT_N is connected to FPGA U1 HP bank 67 QBC pin BL25. Bank 67 VCC1V8 VCCO is nominally 1.8V. Any signal connected to the SMA_CLK_OUTPUT SMA connectors in input mode must be equal to or less than the VCCO for bank 67. This value must be confirmed prior to applying signals to the SMA_CLK_OUTPUT connectors.
Figure 1. User SMA Clock
