In Versal devices, the Adaptable Engine integrated into the PL is configured using CDO files such as rCDO and rNPI. PL CDO mainly contains CFrame data along with PL and NoC power domain initialization commands. NPI contains configuration data related to the NPI blocks. NPI blocks include NoC elements (NMU, NSU, NPS, NCRB), DDR memory controller, XPHY, XPIO, GTY, MMCMs, etc.).
The NPI data is generated by the Vivado tool for the various NPI blocks. The NPI blocks that are present in Versal devices include NoC, DDR memory controller, XPHY, XPIO, GTY, MMCMs, etc. Before loading the PL configuration, ensure that PMC is configured.
Vivado also inserts USR_ACCESS information as a function ID in the RCDO. Bootgen uses this information and populates the Image Header with this function ID. PLM consumes the image header and stores this USR_ACCESS information at address 0xF2014168 while loading this image. Any upper layer software or hardware manager can access the USR_ACCESS information by reading this address.
The following table describes the content of the files, and is useful for debugging
|PL CDO <.rcdo>||
|NPI CDO <.rnpi>||NPI data