Clock Distribution (Gen 3)

RF Data Converter Interface User Guide (UG1309)

Document ID
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1.4 English

The Zynq UltraScale+ RFSoC Gen 3 supports on-chip clock distribution. For more information, see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269).

Click the Clock Distribution button in the overview page to display the page shown in the following figure.

Figure 1. Clock Distribution
Note: The settings on this page should comply with the limitations of the on-chip clock distribution system and PLL.

Each tile has four input fields and a check box for an in-tile PLL, as described here.

Sample Clock (MHz)
Select the desired sampling rate of converters, which can be generated by the in-tile PLL or a forwarded sampling clock from the source tile.
PLL Checkbox
Enable or disable the PLL in this tile.
Reference Clock (MHz)
Enter the reference or a sampling clock, can be from an external input or a forwarded clock from the source tile.
Note: This frequency can be a reference for the in-tile PLL or the frequency of the sampling clock if it is used directly.
Source Tile
Use the drop-down list to select which tile the clock (reference) comes from. Select the tile itself for the external clock input to this tile, or the source tile for a forwarded clock (reference or sampling clock). Select the tile itself for a source tile.
Distribute Clock
Select options to distribute the clock (acting as source tile) and which clock is distributed:
  1. None: select to not distribute the clock.
  2. Input clock: select to distribute the input clock from an external input. This clock can be a low-frequency reference clock or a high-frequency sampling clock.
  3. PLL output clock: select to distribute the clock generated by the in-tile PLL.

An example configuration is shown in the following figure.

Figure 2. Example Clock Distribution Configuration

In this example, two external input clocks (both at 245.76 MHz) are fed to the ADC_Tile_224 and DAC_Tile_228, respectively. All desired RF-ADC clocks are 2457.6 MHz and desired RF-DAC clocks are 4915.2 MHz.

For the RF-ADC group, Tile_224 distributes its PLL output clock to other RF-ADC tiles. For the RF-DAC group, Tile_228 distributes its input reference to all other RF-DAC tiles.

All RF-DAC tiles enable their PLLs to generate the desired sampling clock at 4915.2 MHz.

When the Apply button is clicked, the GUI updates these configurations to the chip, restarts all tiles, reads back status, and updates the GUI. This might take a while and a percentage bar shows the progress.

The following figure shows the tile status based on the clock distribution configurations in this example.

Figure 3. Tile Status Based on Clock Distribution

For RF-ADC, only Tile 0 (Tile_224) PLL is enabled, and PLLs in other tiles are disabled. The green channel status shows they are in operation status because these tiles are forwarded the sampling clock from Tile 0. For RF-DAC, all PLLs are enabled because Tile 0 (Tile_228) forwarded its reference to other tiles. The status of RF-ADCs and RF-DACs reflect the settings in the Clock Distribution page in this example. The PLL status can also be checked in the PLL page for each tile. For Gen 3, the PLL page shows the status only and all the clock configurations rely on this Clock Distribution page, which is different from the PLL page in Gen 1 and Gen 2.