There are different on-chip clock distribution architecture limitations in different RFSoC generations. The user guides for each board show which RF PLLs/tiles are driven from off-chip and which RF PLLs/tiles get clocks from the on-chip clock distribution system.
Gen 1 and 2: see the ZCU111 Evaluation Board User Guide (UG1271) for more information.
Gen 1 and 2 Predefined Mode
In the overview tab, select Clock Settings to open the onboard PLL GUI in the right panel. This GUI allows you to control and set the input and output frequencies for the PLLs that are integrated onto the ZCU111 evaluation board. In the Predefined mode, available frequencies are provided in the drop-down list for RF-ADC and RF-DAC. Choose your options and click Apply. The GUI programs the onboard RFPLLs. If your desired frequency does not appear in the predefined list, then you must use the advanced configuration mode to customize the sample rates.
Gen 1 and Gen 2 Advanced Mode
The Advanced mode accepts the configuration file for the individual clock ICs on your clocking plug-in board. You can choose the .tcs file shipped along with this tool or generate your own configuration files using TICS Pro Software.
Click Advanced to select the desired clock configuration.
In the overview tab, select Clock Settings to open the onboard PLL GUI in the right panel. This GUI allows you to control and set the input and output frequencies for the PLLs mounted on the CLK104 (daughter board of the ZCU216 and ZCU208 boards). Choose your options and click Apply. The GUI programs the onboard RFPLLs.