The RF Analyzer acquires the absolute
values of tile input clocks and sampling clocks from the IP configuration. Consequently,
if the board clocks are different to the initial IP configuration, it is important to
configure the sampling clocks before other operations.
- Click Clock Distribution.
- Select the PLL and configure the clocks based on the board setup.
See Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) for information on the permitted clocking configurations for your RFSoC device.