DDR Bandwidth Write Utilization - 2022.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.2 English

Description

This rule checks if there is low write bandwidth usage of the associated DDR memory bank

Explanation

The write bandwidth usage indicates that the kernel is not writing the data to the DDR memory at the maximum potential. This will impacts the time to write to the DDR memory.

The write bandwidth usage is mainly dependent on transfer rate, which is the total bytes transferred to the DDR memory per bus active time.

Resolution

To improve the read bandwidth usage, improve the total bytes transferred and decrease the maxi bus active time.

To improve the total bytes transferred, increase the port width size on the interface to 512.

To improve the DDR memory per bus active time, use more burst access instead of single access on the AXI.