DDR Bank Connections - 2022.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.2 English

Description

This rule checks the number of compute unit ports connected to all DDR memory banks on the device.

Explanation

Multiple compute unis, when connected to the same DDR bank, share bandwidth among the N compute units. This creates memory stalls on the system and reduces application performance.

Recommendation

Connect different compute units to different DDR memory banks to improve the system performance.