DSP Resource Utilization - 2022.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.2 English

Description

The design requires more DSP resources elements than are available. The total number of DSP blocks required by all kernels is more than the number available on the device.

Explanation

Xilinx FPGAs and programmable SoCs are ideal for high-performance multi-channel applications that can take advantage of massive parallelism available in the FPGA. To best achieve high performance implementations, the FPGA contains special highly optimized DSP blocks. These blocks can implement specific sequences of operations very effectively. On big designs, or when many individual kernels are combined, too many operations might get mapped to DSP blocks which can result in an unfeasible implementation.

Recommendation

Reduce the number of required DSP blocks for all kernels. This can be achieved by improving sharing within a kernel or by actively changing the algorithm implemented by a kernel. DSP blocks are often used to implement multipliers especially large multipliers. Reducing the number of multiplications can also reduce the number of DSPs required. Allowing larger latency will usually allow more sharing.