Description
This rule checks whether device monitors were inserted into a design.
Explanation
Vitis Runtime Library collects profiling data on host applications and
kernels. Capturing the data required for the Profile Summary requires a few steps prior to
running the application. The FPGA binary (xclbin) file is configured for capturing profiling
data by default. However, using the v++ --profile
option
during compilation and linking enables a greater level of detail in the profiling data
captured.
Solution
The user is missing the compile or link switches –profile
to generate the debug IPs.