Device Monitor Insertion - 2022.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.2 English

Description

This rule checks whether device monitors were inserted into a design.

Explanation

Vitis™ Runtime library collects profiling data on host applications and kernels. Capturing the data required for the Profile Summary requires a few steps prior to running the application. The FPGA binary (xclbin) file is configured for capturing profiling data by default. However, using the v++ --profile option during compilation and linking enables a greater level of detail in the profiling data captured. See Vitis Compiler Command for more information on the --profile option.

Solution

The user is missing the compile or link switches –profile to generate the debug IPs.