Kernel Port Data Width - 2022.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.2 English

Description

The data width on the specified port is not optimal.

Explanation

The specific port, that is not scalar based, is not using the optimium data width (512 bit). Kernel arguments are implemented through memory mapped AXI ports.

Except scalar function arguments (called by value) all arguments to the function are implemented through memory mapped AXI ports on the FPGA. To take maximum advantage of the memory mapped interface, the complete 512 bit AXI port width should be used.

Recommendation

If the data width of a port is far less than 512 bits, consider packaging multiple values into a single transfer. The 512 bits can be efficiently packed and unpacked on the receiving side by using a separate process to read and write to the AXI interface. Applying the DATAFLOW pragma to these processes surrounding the actual algorithm results in an efficient implementation.