The design requires more look-up table (LUT) resources than are available. The total number of all LUT resources required by all kernels is more than the number available on the device.
Look-up table resources are the basic elements used in the programmable logic fabric of an FPGA. Except for operations mapped predefined components such as memory accesses and DSPs, any operation implemented in the FPGA is mapped to LUT resources. In some cases, multiple operations can even be combined and implemented by a single LUT.
When this message is issued, the total number of LUTs required to implement the algorithm exceeds the total number available on the device. It is therefore necessary to reduce the number of LUTs required for the implementation of the algorithm.
When LUT resource utilization is too high, it implies that too much logic is required for the implementation of the algorithm. It is always possible that the algorithm might be too complex to implement on the chosen device; however in many cases, it is possible to reduce LUT resource requirements based on datapath width and algorithm description. For example, is the range of possible values for a variable really integer? Often status variables and counters can only represent a fixed set of values much less than 32 bits. Using this reduced bit-width makes any operation utilizing this variable use much less LUT resources, therefore considerably reducing the LUT usage. In many cases, it is good to study the resource requirements and align them as needed with bit accurate datatypes.