Synchronous Storage Resource Utilization - 2022.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.2 English

Description

The design requires more synchronous storage elements than are available. The total number of registers required by all kernels is more than the number available on the device.

Explanation

CPUs contain an internal set of registers keeping input and output values of the basic operations of the arithmetic logical unit. When an algorithm is implemented in hardware on and the FPGA, storage of intermediate values is required if the sequence of operations spawns multiple cycles. As a result, any design but the simplest require registers for intermediate value storage.

The number of registers, or synchronous storage elements, exceeds the number available on the device. Reduce the number of registers required for the algorithm implementation.

Recommendation

Reduce the number of registers required for the algorithm implementation, and there are many ways to influence the register count of an implementation:

  1. Take note of the number of registers are used and where. You can find this information in the HLS report or by studying the dependencies in the HLS Schedule viewer.
  2. With this information, you can decide whether restructuring the algorithm, mapping registers to memory, or reducing the datapath width would best reduce the overall resource use.