Board Features

VCK190 Evaluation Board User Guide (UG1366)

Document ID
UG1366
Release Date
2023-03-17
Revision
1.1 English

The VCK190 evaluation board features are listed here. Detailed information for each feature is provided in Board Component Descriptions.

  • XCVC1902, VSVA2197 package
  • Form factor: extended height PCIe® , double-slot (heatsink clearance)
  • Onboard configuration from:
    • USB-to-JTAG bridge
    • JTAG pod 2 mm 2x7 flat cable connector
    • microSD card (PS MIO I/F)
    • microSD card (System Controller I/F)
  • External boot module (EBM) configuration option
    • X-EBM-01 dual quad SPI (QSPI)
      • 2x1 Gb MT25QU01GBBB8E12-0SIT
  • Clocks
    • ACAP Bank 406 HDMI_REC_CLK_OUT 148.50 MHz
    • ACAP Bank 503 RTC Xtal 32.768 kHz
    • ACAP Bank 503 Si570 REF_CLK 33.3333 MHz
    • ACAP Bank 700 Si570 DDR4_CLK (DIMM) 200 MHz
    • ACAP Bank 705 Si570 DDR4_CLK2 (LPDDR4) 200 MHz
    • ACAP Bank 711 Si570 DDR4_CLK1 (LPDDR4) 200 MHz
    • ACAP Bank GTY103/4 (REFCLK0) PCIe_CLK0/1 100 MHz
    • ACAP Bank GTY105 (REFCLK0) Si570 zSFP_SI570_CLK 156.250 MHz
    • ACAP Bank GTY105 (REFCLK1) Si570 HSDP_SI570_CLK 156.250 MHz
    • ACAP Bank GTY200 (REFCLK0) 8A34001_CLK1_IN 100 MHz
    • IEEE-1588 eCPRI 8A34001 clocks (various)
  • DDR4 8 GB 72-bit (64-bit, and 8-bit ECC) UDIMM
    • XPIO triplet 1 (banks 700, 701, 702)
  • Two LPDDR4 interfaces (2x32-bit 4 GB components each)
    • XPIO triplets 2 (banks 703, 704, 705) and 4 (banks 709, 710, 711)
  • PL FMCP HSPC (FMC+) connectivity
    • XPIO triplet 3 (banks 706, 707, 708)
    • FMCP1 HSPC full LA[00:33] bus
    • FMCP2 HSPC full LA[00:33] bus
  • PL GPIO connections
    • PL UART1 to FTDI
    • PL GPIO DIP switch (4-position)
    • PL GPIO pushbuttons (two)
    • PL GPIO LEDs (four)
    • PL GPIO DC configuration header
    • PL SYSCTLR_GPIO[0:5]
  • 44 PL GTY transceivers (11 quads)
    • PCIe 8-lane edge connector (8, banks GTY103, GTY104)
    • HSDP USB3.1 TYPE C (1, bank GTY105)
    • zSFP28 (2, bank GTY105)
    • HDMI (3, bank GTY106)
    • HDMI TX only, RX not used (1, bank GTY106)
    • zQSFP28 (4, bank GTY200)
    • FMCP1 HSPC DP (12, banks GTY201-GTY203)
    • FMCP2 HSPC DP (12, banks GTY204-GTY206)
    • Not used (1, bank GTY105)
  • PCI Express endpoint connectivity
    • Gen1 8-lane (x8)
    • Gen2 8-lane (x8)
    • Gen3 8-lane (x8)
    • Gen4 8-lane (x8)
  • PS PMC MIO connectivity
    • PS MIO[0:12]: boot configuration header
      • DC QSPI support
    • PS MIO[13:25]: USB2.0
    • PS MIO[26:36, 50:51]: SD1 I/F
    • PS MIO[37]: ZU4_TRIGGER
    • PS MIO[38:39]: PCIe_WAKE_B, PCIe_PERST_B
    • PS MIO[40:41]: CAN1
    • PS MIO[42:43]: UART0 to FTDI
    • PS MIO[44:47]: I2C1, I2C0
    • PS MIO[48:49], PS LPD MIO[0:25]: dual GEM0/1 RGMII Ethernet with stacked RJ-45
  • Security: PSBATT button battery backup
  • SYSMON header
  • Operational switches (power on/off, PROG_B, boot mode DIP switch)
  • Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
  • Power management
  • System Controller (XCZU4EG)

The VCK190 provides a rapid prototyping platform using the XCVC1902-2VSVA2197 device. See the Versal Architecture and Product Data Sheet: Overview (DS950) for a feature set overview, description, and ordering information.