LPDDR4 Component Memory

VCK190 Evaluation Board User Guide (UG1366)

Document ID
UG1366
Release Date
2023-03-17
Revision
1.1 English

[Figure 1, callout 3 and 4]

The VCK190 board hosts two LPDDR4 memory systems, each with a component configuration of 2x (1x32-bit component).

Figure 1. LPDDR4 Component Memory

XCVC1902 U1 XPIO triplet 2 (banks 703/704/705) and triplet 4 (banks 709/710/711) each support two independent 32-bit 2 GB component interfaces (4 GB per triplet).

  • Manufacturer: Micron
  • Part number: MT53D512M32D2DS-046 WT:D (dual die LPDDR4 SRAM)
  • Component description
    • 16 Gb (512 Mb x 32)
    • 1.1V 200-ball WFBGA
    • DDR4-2133

The VCK190 XCVC1902 ACAP PL DDR interface performance is documented in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957). The VCK190 board LPDDR4 component memory interfaces adhere to the constraints guidelines documented in the PCB guidelines for DDR4 section of Versal ACAP PCB Design User Guide (UG863). The VCK190 DDR4 component interface is a 40Ω impedance implementation. Other memory interface details are also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more memory component details, see the Micron MT53D512M32D2DS data sheet at the Micron website. The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Xilinx Design Constraints.