PCIe Clock

VCK190 Evaluation Board User Guide (UG1366)

Document ID
UG1366
Release Date
2023-03-17
Revision
1.1 English

[Figure 1, callout 41]

The VCK190 board includes an IDT 85411 (U39) 1:2 clock buffer for the PCIe clock fan out to the Versal ACAP. The 100 MHz PCIE_CLK_P/N clock from the PCIe 8-lane edge connector (P3) drives the U39 clock input.

The U39's buffered outputs are used to create differential clock pairs to the ACAP U1 GTY103/GTY104 PCIe interface:

  • U39's Q0 PCIE_CLK0_P/N are connected to PCIE_TX/RX[0:3] interface GTY103 GTY_REFCLK0 pins W39 (P) and W40 (N), which are A/C coupled
  • U39's Q1 PCIE_CLK1_P/N are connected to PCIE_TX/RX[4:7] interface GTY104 GTY_REFCLK0 pins R39 (P) and R40 (N), which are A/C coupled
  • 1:2 clock buffer
    • Q0: 100 MHz LVDS
    • Q1: 100 MHz LVDS