[Figure 1, callout 25]
The ACAP PS bank 501 MIO40 (TX OUT) and MIO41 (RX IN) support the PS-side CAN bus TX and RX interface wired through the TI SN74AVC2T244 level-translators U107 and U109, respectively, to the NXP TJA1057GT/3J CAN-bus transceiver U110. This transceiver is connected to the 2x4 0.1-inch pitch 8-pin male header J5.
See the NXP TJA1057GT/3J data sheet at the Nexperia website for CAN-bus transceiver details.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Xilinx Design Constraints.