[Figure 1, callout 36]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U2) connected to the GC inputs of U1 DDR4 DIMM interface bank 700. The DDR4_DIMM1_CLK_P and DDR4_DIMM1_CLK _N series capacitor coupled clock signals are connected to XCVC1902 ACAP U1 pins AE42 and AF43, respectively. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 200.000 MHz.
- Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 200.000 MHz default)
- I2C address
0x60 - LVDS differential output, total stability: 61.5 ppm