[Figure 1, callout 35]
POR_B is the Versal ACAP processor reset, which can be controlled by:
- SYSCTLR (U125)
- PC4 header (J36)
- MIO EBM (external boot module on J212)
- FTDI USB JTAG chip (U20)
In the following figure, U235 allows directional open drain level shifting for all of these masters, and J326 allows them to be bused together if desired. The fifth channel buffers POR_B out to the EBM (external boot module) as DC_PS_POR_B. The TPS389001 U10 supervisor chip holds POR_B off until power is valid. The VCK190 board POR circuit is shown in the figure.
Figure 1. POR_B Reset Circuit
